Bug(?) VHDL UML class diagrams contain libraries and use clauses as members

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Bug(?) VHDL UML class diagrams contain libraries and use clauses as members

Stefan Dröge
Hi everyone,
I am using doxygen to document my VHDL code, and I activated the "UML_LOOK = YES" option, to generate UML style diagrams.
I noticed, that the Libraries (like "ieee") and Use Clauses (like std_logic_1164) are listed as public members in the diagrams (see attached image, or github project, below). In my opinion they should be treated like "#include" statements in C.

I have provided an example project here: https://github.com/StefanD986/doxygen_vhdl_bug_example

You don't need any vhdl compiler to test it. Just clone and build the doxygen documentation in doc/.

-- Stefan

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