Bug(?) VHDL UML class diagrams contain libraries and use clauses as members
I am using doxygen to document my VHDL code, and I activated the "UML_LOOK = YES" option, to generate UML style diagrams.
I noticed, that the Libraries (like "ieee") and Use Clauses (like std_logic_1164) are listed as public members in the diagrams (see attached image, or github project, below). In my opinion they should be treated like "#include" statements in C.