VHDL Function and '=>' Token

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VHDL Function and '=>' Token


Anyone know why Doxygen does not create links to VHDL Functions?  Here is a simple example:

 packapackage MyLib_General_Purpose is

    2 end package MyLib_General_Purpose;

    3 package body MyLib_General_Purpose is

    4  function resize_and_clip(bits: integer) return signed is

    b begin

   10  end function;

   11  end package body MyLib_General_Purpose;


   13 entity test is

   14 end entity test;

   15 architecture test1 of test is

   16  signal ReturnValue : signed;

   17 begin

   18  ReturnValue <= resize_and_clip(1);

   19 end architecture test1;


(Doxygen was run with the generic config, except “optimize for VHDL” is enabled.  )

I would expect to see a link from resize_and_clip(1) and to resize_and_clip(bits: integer). 

I’ve tried function in C code and doxygen creates links to those just fine.


I suspect the problem has something to do with this line in the vhdlparserjj file which seems to treat it as a “Generic”:


But, I don’t understand the addVhdlType function well enough to know how to fix it.



Also, does anyone know how to fix this error with the precedence for the ‘=>’ token?

Either of these lines work:
    variable max_clipped_value: signed(1 downto 0) := ((bits-1) => '0', others => '1');

    variable max_clipped_value: signed(1 downto 0) := (1 => '0', others => '1');


But, this one throws an error on the “=>” symbole

    variable max_clipped_value: signed(bits-1 downto 0) := (bits-1 => '0', others => '1');


I’ve found and fixed many issues with the vhdlparser.jj file (mostly around the “generate-else” syntax), but I have not solved this one.






(Just in case the HTML code above becomes unreadable in the mailing list, here is the raw text)

package MyLib_General_Purpose is

end package MyLib_General_Purpose;

package body MyLib_General_Purpose is

  function resize_and_clip(bits: integer) return signed is


 end function;      

end package body MyLib_General_Purpose;


entity test is

end entity test;

architecture test1 of test is

signal ReturnValue : signed;


ReturnValue <= resize_and_clip(1);

end architecture test1;


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