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VHDL Hierachy

Martyn Pittuck

Hello,

 

I recently had upgraded a doxygen install to the current release and instantly lost all the hierarchy information within the documentation. Trying different versions of doxygen the problem seems to have started after Release 1.8.7 when the parser was changed, all releases after that tag result in the same issue:

 

Some code:

 

library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all;

library lib;

 

entity a_module is

            port ( a_in : in std_logic; a_out : out std_logic);

end a_module;

 

architecture behavioral of a_module is

            signal b_in                  : std_logic;

            signal b_out    : std_logic;

            signal c_in                   : std_logic;

            signal c_out     : std_logic;

begin

 

            b_i : entity work.b_module

            port map (b_in => b_in, b_out => b_out);

 

            c_i : entity lib.c_module

            port map (c_in => c_in, c_out => c_out);

 

end behavioral;

 

library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all;

 

entity b_module is

            port ( b_in : in std_logic; b_out : out std_logic);

end b_module;

 

architecture behavioral of b_module is

            signal b_in : std_logic;

            signal b_out : std_logic;

begin

            b_out <= b_in;

end behavioral;

 

[c_module is the same code as b_module, just located in a different place]

 

Older version of doxygen identify a_module as using b_module and c_module, newer versions do not. The entities a_module and b_module are in the 'work' scope, c_module is partially compiled elsewhere. 

 

Is there any way to fix this or is there a way to force the class hierarchy. My only option at the moment is to require my user nothing new than 1.8.7 which is not ideal...

 

Many thanks,

 

 - Martyn

 


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Re: VHDL Hierachy

Martyn Pittuck

Hey Stefan,

 

I have uploaded some sample code to http://github.com/martynp/doxygen_vhdl_test/. I tried your settings file and it did not work still…

 

With doxygen 1.8.5 (CentOS 7 default version):

 

https://github.com/martynp/doxygen_vhdl_test/blob/master/1.8.5.png

 

With doxygen 1.8.12:

 

https://github.com/martynp/doxygen_vhdl_test/blob/master/1.8.12.png

 

I had a play with most of the settings I could find – but doxygen is not figuring out the entity relationships. It works if I use components, but I would rather not (there are auto-generated parts of the code which will not work without major changes).

 

Thanks!

 

-          Martyn

 

From: [hidden email] [mailto:[hidden email]] On Behalf Of Stefan Dröge
Sent: 03 June 2016 10:17
To: Martyn Pittuck <[hidden email]>
Cc: [hidden email]
Subject: Re: [Doxygen-users] VHDL Hierachy

 

With hierarchy you mean something like that the diagram below? That was generated for my VHDL code with doxygen Version 1.8.11 and the attached Doxyfile.

 

(In case attachements do not work on the mailinglist here is a link: https://www.dropbox.com/s/pdpybkpstxx73uq/Screenshot%202016-06-03%2011.08.24.png?dl=0 )

 

2016-06-03 9:55 GMT+02:00 Martyn Pittuck <[hidden email]>:

Hello, 

 - Martyn

 


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Re: VHDL Hierachy

Stefan Dröge
True, now that you mention it I remember that I also had two entities
that didn't show up in the graph at first, because I also used
direct-instantiation for the two missing entities. I usually never do
that, only for these two missing entities I was too lazy. (What I
usually do is I add the component declarations to a package, which I
include at the top of my file. That gives a better overview what is
used in the entity, but also keeps the architecture declarative part
clean.)

I just added the component declarations of my two missing entities to
the package that I include, and changed the instantiation and that
solved it for me. But if "a_module" is auto-generated I guess thats
not an option for you.

On the other hand: If a_module is auto-generated, you cannot add
doxygen comments to it. And since its generated, the inner structure
of a_module shouldn't be of concern anyway, in my opinion. Instead
maybe the settings/options of the generating script/program should be
documented.

But yeah, I know what you mean. I try to avoid generated code as much
as possible. But there is not always a way around it.

And it definitely is a bug in the doxygen parser. (Sadly Doxygen for
VHDL is not very good anyway (e.g. the UML class diagrams are almost
useless). Unfortunately there are no real alternative I guess.

2016-06-03 18:51 GMT+02:00  <[hidden email]>:

> Hey Stefan,
>
>
>
> I have uploaded some sample code to
> http://github.com/martynp/doxygen_vhdl_test/. I tried your settings file and
> it did not work still…
>
>
>
> With doxygen 1.8.5 (CentOS 7 default version):
>
>
>
> https://github.com/martynp/doxygen_vhdl_test/blob/master/1.8.5.png
>
>
>
> With doxygen 1.8.12:
>
>
>
> https://github.com/martynp/doxygen_vhdl_test/blob/master/1.8.12.png
>
>
>
> I had a play with most of the settings I could find – but doxygen is not
> figuring out the entity relationships. It works if I use components, but I
> would rather not (there are auto-generated parts of the code which will not
> work without major changes).
>
>
>
> Thanks!
>
>
>
> -          Martyn
>
>
>
> From: [hidden email] [mailto:[hidden email]] On Behalf Of Stefan
> Dröge
> Sent: 03 June 2016 10:17
> To: Martyn Pittuck <[hidden email]>
> Cc: [hidden email]
> Subject: Re: [Doxygen-users] VHDL Hierachy
>
>
>
> With hierarchy you mean something like that the diagram below? That was
> generated for my VHDL code with doxygen Version 1.8.11 and the attached
> Doxyfile.
>
>
>
> (In case attachements do not work on the mailinglist here is a link:
> https://www.dropbox.com/s/pdpybkpstxx73uq/Screenshot%202016-06-03%2011.08.24.png?dl=0
> )
>
>
>
> 2016-06-03 9:55 GMT+02:00 Martyn Pittuck <[hidden email]>:
>
> Hello,
>
>  - Martyn
>
>
>
>
> ------------------------------------------------------------------------------
> What NetFlow Analyzer can do for you? Monitors network bandwidth and traffic
> patterns at an interface-level. Reveals which users, apps, and protocols are
> consuming the most bandwidth. Provides multi-vendor support for NetFlow,
> J-Flow, sFlow and other flows. Make informed decisions using capacity
> planning reports. https://ad.doubleclick.net/ddm/clk/305295220;132659582;e
> _______________________________________________
> Doxygen-users mailing list
> [hidden email]
> https://lists.sourceforge.net/lists/listinfo/doxygen-users
>
>

------------------------------------------------------------------------------
What NetFlow Analyzer can do for you? Monitors network bandwidth and traffic
patterns at an interface-level. Reveals which users, apps, and protocols are
consuming the most bandwidth. Provides multi-vendor support for NetFlow,
J-Flow, sFlow and other flows. Make informed decisions using capacity
planning reports. https://ad.doubleclick.net/ddm/clk/305295220;132659582;e
_______________________________________________
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